搜索资源列表
MIPS
- MIPS处理器的顶层VHDL代码，可综合，可仿真，属硬件描述语言，集成电路设计代码
MIPScpu
- MIPS处理器VHDL代码，实现加法，减法乘除等运算，可综合-MIpscup vith vhdl
DES
- DES加密算法的VHDL实现,采用流水线技术实现-The VHDL implement of DES encrypt algorithmic
singlecycle_mips
- single cycle mips design by verilog.
m1_core.tar
- 一个小巧的mips处理器，verilog写的，大家可以-A small mips processor, verilog written, we can see
mipscpu-source
- mips cpu的实现.MIPS是世界上很流行的一种RISC处理器。MIPS公司的R系列就是在此基础上开发的RISC工业产品的微处理器。这些系列产品为很多计算机公司采用构成各种工作站和计算 机系统。 -mips cpu implementation. MIPS is the world' s very popular as a RISC processor. MIPS company' s R series is based on the development of industr
microprocessor
- 一个微处理器的Verilog代码，根据英文书籍《数字设计与架构》中的例子而写，能够运行MIPS指令，能正确执行跳转指令。通过modelsim仿真，含测试代码。-Verilog code for a microprocessor, according to the English book " Digital Design and Architecture" was written in the example, to run MIPS instructions to jump
mips
- MIPs CPU，VERILOG代码，经过QUARTUS综合，时序分析，验证无误。-MIPS CPU
PipelineCPU
- Quartus II 7.2环境中，采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计-quartusII mips pipeline 32bit cpu design
singleCycleProc
- 简化的单时钟循环VHDL处理器.可以运行一些简单的mips指令，例如add, sub, and, or, slt, beq and j. -A simplified single cycle processor in VHDL. This processor can continuously execute some simple MIPS instructions which are lw, sw, add, sub, and, or, slt, beq and j.
vhdl-pipeline-mips_latest.tar
- pipeline mips in vhdl
project3
- mips single cycle cpu
MIPS
- 用VHDL设计单周期的MIPS处理器,实现简单的指令-VHDL design with single-cycle MIPS processor, simple instructions
mips-cpu
- 单周期的mips处理器设计，用vhdl语言实现各个模块的功能-Single-cycle mips processor design, using vhdl language functions of each module
VHDL-for-Datapath
- MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd - memory buffer.vhd - buffer ALUcon.vhd - Alu controller pc.vhd - program counter REG - reg
mips-VHDL
- 自己作业代码，应用VHDL语言实现一个多周期的简单MIPS核-AlphaJob code, the application of VHDL language more than one cycle of a simple MIPS core
vhdl-pipeline-mips0
- MIPS CPU WITH PIPELINE procesador MIPS-FZA -- Autor: mahdi ahmadi -- Email: mahdi@fza.ir -- mahdifza@yahoo.com -- -- Version: 1.0
vhdl-pipeline-mips_latest
- pip-lined MIPS in vhdl
MIPSSYN
- MIPS vhdl code. 8 files in
mips
- implement of mips data path in single cycle with vhdl language